Our group develops high-end FPGA-based systems. The systems consist of a massive signal processing and a variety of different interfaces. The employed FPGAs bridge the entire architecture and consequently the FPGA designs have multiple clock domains. A few years ago the multiple-clock domain systems became a standard architecture in our products. We identified a need in a special treatment for CDC problems due to inability of standard tools to cover the CDC problems, and due to multiple designer bugs that appeared in the designs with the multiple clocks. We evaluated a number of leading CDC tools and we chose vSync Circuits Tool Kit as a main tooling for CDC treatment starting from the design stage, through simulations and down to static verification of the product before starting the lab testing.

During the last two years the tool kit components are gradually employed in our group. The tool kit is successfully employed both for legacy and new designs, identifying bugs in the existing systems and improving the design stability for new designs by employing the vGenerator solutions. The reset synchronization module of vSync (vReset) is employed in every new project along with other synchronizer types produced by vGenerator and this employment becomes more and more common with time.

vChecker tool is very easy to use, with a convenient bug tracking and cross reference abilities, allowing fast problem understanding and fixing. At the beginning we questioned the tool kit maturity, however, right at the beginning we understood that technically vChecker identifies all the existing problems. During the last two years, vSync Circuits engineers have accompanied our engineers very closely, continuously looking for ways of improving the tools in the next versions. This way of work led to mature tools through multiple frequently released versions. The provided support is very responsive, and along with on-site training conducted by vSync Circuits, it enabled a good adoption of the tools inside our group.

The tool kit components are incorporated nicely into our design flow, and the methodology of using the tools along the design flow by itself prevents in many cases CDC problems. The tools are friendly and significantly reduce the amount of CDC related bugs before entering the lab.

To summarize, we are highly satisfied by vSync Circuits tool kit both at the technical level (problems identification, solution generation) and also at the user experience level. The tool kit realizes our group concept change for FPGA development, consisting of preparation of a highly verified design before lab testing stage start, and of minimizing the verification done by means of lab testing.