Field Applications Engineer (FAE)
Core Responsibilities:
- Provide technical support to the customers
- Work closely with software developers to define new features and directions
- Verify functionality through simulation, debugging and formal equivalence checking
Job Requirements
- BS Electrical Engineering
- Proficiency in RTL design and/or RTL functional verification
- 3-5 years of experience in design and verification tools
- Practical knowledge of both Verilog and VHDL languages
- Experience in simulation test benches and design verification
- Good communication skills
Senior Software Developer
Core Responsibilities:
- Develop/create applications/tools in C, C++
- Perform porting existing applications
- Develop new tests to improve functional/code coverage
Job Requirements:
- BS/MS in Computer Engineering
- Strong software design skills
- Excellent knowledge of C, C++
- Practical knowledge of both Verilog and VHDL languages
- Hands on experience in Python scripting and makefile
- Basic understanding of RTL design
Careers
vSync Circuits
Our Products
vSync Circuits delivers a variety of EDA and IP solutions for ASIC and FPGA verification and integration. vSync Circuits CDC verification is comple-mented by vSync Circuits intellectual property (IP) cores portfolio with multiple highly configurable fool-proof synchronizers, enabling not only CDC analysis, but also multiple clock domain design integration and bug-fix. In addition to the static analysis, vSync Circuits platforms support different ASIC and FPGA design flows, including ASIC and FPGA simulations at RTL and gate-level. vSync Circuits EDA tools enable fast design timing analysis, design reliability assessment (MTBF) and an automated bug fixing.
About vSync Circuits
vSync Circuits is an EDA and IP solutions company, providing integration and verification solutions for ASIC and FPGA design and verification groups. The company introduces a novel and unique technology for reliable multiple clock-domain design integration and CDC verification, comprising of a tool-based approach, which bridges the design and verification worlds. vSync Circuits methodology is based on the concept of combined employment of structural and formal verification, RTL and gate-level verification, automatic timing constraints generation and an automatic bug-fix. vSync Circuits methodology is generic and is compatible with both FPGA and ASIC verification and integration flows.