- R. Dobkin, D. Alon, Combining CDC Analysis and STA Tools for MCD SoC Verification, SNUG 2011.
- I. Schwartz, A. Teman, R. Dobkin, A. Fish, “Near-Threshold 40nm Supply Feedback C-Element,” ASQED 2011.
- S. Beer, R. Ginosar, M. Priel, R. Dobkin, A. Kolodny, “An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm“, ISCAS, pp. 2593-2596, 2011.
- R. Dobkin, “Synchronization Issues in Multiple-Clock Domain Designs,” ChipEx, 2010.
- A. Tamam, R. Dobkin, O. Maltz, L. Zahavi, E. Pecht, M. Peleg, “Implementation of Interference Rejection for OFDM Communications,” Israel IEEE Conf., 2010.
- S. Beer, R. Dobkin, M. Priel, R. Ginosar, A. Kolodny, “The Devolution of Synchronizers,” Proc. of ASYNC, pp. 94-103, 2010.
- R. Dobkin, “Asynchronous reset synchronization and distribution – challenges and solutions,” www.embedded.com, 2017.
- R. Dobkin, “FIFOs mit asynchronen Eingangs- und Ausgangs-Taktraten,” ELEKTRONIKPRAXIS, 2018.
vSync Circuits delivers a variety of EDA and IP solutions for ASIC and FPGA verification and integration. vSync Circuits CDC verification is comple-mented by vSync Circuits intellectual property (IP) cores portfolio with multiple highly configurable fool-proof synchronizers, enabling not only CDC analysis, but also multiple clock domain design integration and bug-fix. In addition to the static analysis, vSync Circuits platforms support different ASIC and FPGA design flows, including ASIC and FPGA simulations at RTL and gate-level. vSync Circuits EDA tools enable fast design timing analysis, design reliability assessment (MTBF) and an automated bug fixing.
About vSync Circuits
vSync Circuits is an EDA and IP solutions company, providing integration and verification solutions for ASIC and FPGA design and verification groups. The company introduces a novel and unique technology for reliable multiple clock-domain design integration and CDC verification, comprising of a tool-based approach, which bridges the design and verification worlds. vSync Circuits methodology is based on the concept of combined employment of structural and formal verification, RTL and gate-level verification, automatic timing constraints generation and an automatic bug-fix. vSync Circuits methodology is generic and is compatible with both FPGA and ASIC verification and integration flows.