- ...We evaluated a number of leading CDC tools and we chose vSync Circuits Vincent Platform as a main tooling for CDC treatment starting from the design stage, through simulations and down to static verification of the product before starting the lab testing. ...Vincent Platform is successfully employed both for legacy and new designs, identifying bugs in the existing systems and improving the design stability for new designs by employing the vGenerator solutions. ...vChecker tool is very easy to use, with a convenient bug tracking and cross reference abilities, allowing fast problem understanding and fixing. ...The provided support is very responsive, and along with on-site training conducted by vSync Circuits, it enabled a good adoption of the tools inside our group. ...To summarize, we are highly satisfied by vSync Circuits tool kit both at the technical level (problems identification, solution generation) and also at the user experience level.~ Israel Samuha, FPGA Group Manager, Rafael
- We used the vChecker tool in a project with national importance to Israel's security and safety. The one week we dedicated to learning the tool and solving the CDC problems in the design saved us about 2 months or more in integration and a non-quantified amount of time in production and experiments.~ I.Sh., Board and Logic Design Team Leader, Rafael
- We looked for a tool to help debug clock domain crossing issues in our FPGA designs. We encountered vSync, a small yet dynamic and innovative company. We are genuinely impressed with the vSync toolset. In many aspects we found it to be significantly better than products offered by the larger companies, and with a significantly lower price tag. As far as customer support goes, the response time is very fast and support quality is excellent. vSync helped us to efficiently discover and debug CDC issues and thus cut down significantly on development time.~ Avshalom Elyada, FPGA Architecture Lead, GE Healthcare CV-ULS Israel
- Our group develops high-end FPGA-based systems. The systems consist of a massive signal processing and a variety of different interfaces. The employed FPGAs bridge the entire architecture and consequently the FPGA designs have multiple clock domains. A few years ago the multiple-clock domain systems became a standard architecture in our products. We identified a need in a special treatment for CDC problems due to inability of standard tools to cover the CDC problems, and due to multiple designer bugs that appeared in the designs with the multiple clocks. We evaluated a number of leading CDC tools and we chose vSync Circuits Tool Kit as a main tooling for CDC treatment starting from the design stage, through simulations and down to static verification of the product before starting the lab testing. During the last two years the tool kit components are gradually employed in our group. The tool kit is successfully employed both for legacy and new designs, identifying bugs in the existing systems and improving the design stability for new designs by employing the vGenerator solutions. The reset synchronization module of vSync (vReset) is employed in every new project along with other synchronizer types produced by vGenerator and this employment becomes more and more common with time. vChecker tool is very easy to use, with a convenient bug tracking and cross reference abilities, allowing fast problem understanding and fixing. At the beginning we questioned the tool kit maturity, however, right at the beginning we understood that technically vChecker identifies all the existing problems. During the last two years, vSync Circuits engineers have accompanied our engineers very closely, continuously looking for ways of improving the tools in the next versions. This way of work led to mature tools through multiple frequently released versions. The provided support is very responsive, and along with on-site training conducted by vSync Circuits, it enabled a good adoption of the tools inside our group. The tool kit components are incorporated nicely into our design flow, and the methodology of using the tools along the design flow by itself prevents in many cases CDC problems. The tools are friendly and significantly reduce the amount of CDC related bugs before entering the lab. To summarize, we are highly satisfied by vSync Circuits tool kit both at the technical level (problems identification, solution generation) and also at the user experience level. The tool kit realizes our group concept change for FPGA development, consisting of preparation of a highly verified design before lab testing stage start, and of minimizing the verification done by means of lab testing.~ Israel Samuha, FPGA Group Manager, Rafael
- We employed vSync tools at a late stage of our ASIC project, and discovered serious CDC problems that would have led to a complete malfunctioning of the product. The problems were discovered by vChecker at the pre-fabrication stage of the design, and in order to save time, we solved them by rerouting and constraining inside the final P&R netlist database. The employment of vSync platform allowed us to avoid re-fabrication, saving a lot of money and time.~ Dov Alon, VP of Engineering, Ramon Chips Ltd.
- We employed vSync Vincent platform for verification and constraining of our complex digital ASIC design, which was also deployed and tested on a FPGA platform. While we started employing Vincent platform when the design was partially mature, it helped us to discover many linting-level problems, which we did not notice before. After we cleaned the code, we analyzed CDC problems reported by Vincent platform for our design and fixed many real issues. We also upgraded our simulation environment with vSync Simulation library, and realized the benefits of Vincent platform dynamic simulation. During the work vSync provided us with a very responsive and competent support. Vincent platform helps us to assure our design reliability and we find the platform essential to deliver correct functionality of ASIC and FPGA designs.~ Avi Katz, Vice President R&D, Senso Optics Ltd.
- We employed Vincent platform tool chain on our partially mature design and immediately discovered bugs that appeared, but were not yet understood and solved in the lab. The early bugs discovery and easy tracking using vSync tools, allowed us to save valuable time and to stabilize our product more quickly. Vincent platform tool chain is now an integral part of our standard design flow, shortening our design cycle and assuring a correct design functionality.~ Shay Iline, Technical leader, Compass-EOS
- We employ vSync tools and libraries as a part of our ASIC verification sign-off cycle. vSync methodology allows us to discover and manage multiple design flaws, including an efficient management of third-party IPs. vSync team works closely with us, providing a timely and valuable support. The employment of vSync Vincent platform allows us to assure high design reliability and shortens our time to market.~ Niv Margalit, Director of VLSI, Compass-EOS
Vincent Platform consists of a number EDA tools and IP module libraries, enabling reliable integration and verification of multiple-clock domain designs.
vGenerator produces reliable glue logic, offering a variety of synchronization solutions for different system requirements
vChecker is a Static Clock Domain Crossing (CDC) verification and CDC management tool
vTest is a regression tests management tool
vSync Simulation and Synthesis libraries are employed for verification and synthesis of Multiple Clock Domain designs, integrated by Vincent Platform